1. Field of the Invention
The invention relates to a method of fabricating device isolation structures, and more particularly to a method of fabricating shallow trench isolation structures.
2. Description of the Related Art
A variety of integrated circuits incorporate device isolation structures between adjacent semiconductor transistors to prevent short circuits between the adjacent transistors. An insulating layer for isolating devices needs to be formed between adjacent transistors. This can be done by forming a shallow trench isolation structure, that define the active areas of devices.
FIGS. 1A-1E schematically illustrate processing steps in the conventional method of forming a trench isolation structure. Referring to FIG. 1A, a substrate 10 having a pad oxide layer 11 formed thereon by thermal oxidation is provided. The pad oxide layer 11, for example, a silicon oxide layer is covered with a silicon nitride layer 12 deposited by plasma enhanced chemical vapor deposition (PECVD).
Referring to FIG. 1B, the silicon nitride layer 12 is covered with a layer of photoresist 13, and defined by conventional photolithography. The silicon nitride layer 12 is anisotropically etched to expose the surface of the pad oxide layer 11. Similarly, the pad oxide layer 11 and the substrate 10 are defined and etched through. The pad oxide layer 11 is penetrated through and a portion of the substrate 10 is removed. Thus a trench 14 is formed in the substrate 10.
Next, the photoresist 13 is stripped to expose the defined silicon nitride layer 12a. The trench 14 within the substrate 10 is covered with a liner oxide layer 16 grown by thermal oxidation at a high temperature, as shown in FIG. 1C. The trench 14 is overfilled with a layer of silicon oxide 15 so that the silicon oxide layer 15 extends over the surface of the silicon nitride layer 12a. Using the silicon nitride layer 12a as a stop layer, chemical mechanical polishing is performed to etch back the silicon oxide layer 15 until the surface of the silicon nitride layer 12a is exposed. Thus an oxide plug 15a structure is formed as show in FIG. 1D.
Referring to FIG. 1E, both the silicon nitride layer 12a and the pad oxide layer 11a are removed, respectively. The pad oxide layer 11a is etched by wet etching, for example, dipping the pad oxide layer in a hydrogen fluoride solution. The isolation structure of the device is accomplished.
In the process as described above, wet etching is used to remove the pad oxide layer 11 a with hydrofluoric acid solution as an etchant. During isotropic etching, the surface of the oxide plug 15a adjacent the substrate 10 is overetched due to the isotropic etching by the hydrofluoric acid. A recess 17 is thus produced on the sidewall of the trench.
Additionally, a sacrificial oxide layer used to protect the surface of the substrate typically is formed over the surface of the substrate after forming the device isolation region. The sacrificial oxide layer is removed by hydrofluoric acid solution and overetching may still cause a recess on the oxide plug adjacent to the surface of the substrate correspondingly.
When the semiconductor device is completed, the charges caused by overetching accumulating in the recess formed on the oxide layer adjacent to the substrate, reduces the threshold voltage of the transistor and produces the abnormal sub-threshold current associated with the "kink effect". Occurrence of the kink effect impairs device and circuit performance and is thus undesirable.